Correlated Double Sampling

Correlated Double Sampling, or CDS, is a method employed to improve the signal to noise ratio (S/N) of integrating image sensors. By subtracting a pixel's dark or reference output level from the actual light-induced signal, static fixed pattern noise (FPN) and several types of temporal noise are effectively removed from the sensor's output.

In an optical sensor the photocharge is generally collected on a capacitor. The signal amplitude is read as the voltage over that capacitor (V=Q/C). With the CDS procedure the signal voltage Vs=Qs/C is compared with the "dark" or "empty" or "reset" level voltage Vr = Qr/C that is obtained when all charges of C have been channeled off to a fixed potential. Thus for each pixel the final output V = Vs-Vc = (Qs-Qr)/C.

Spatial and temporal noises that are common to Vr and Vs disappear from the result:

  • fixed pattern noise (spatial noise, static non-uniformity)
  • KTC noise of the photodiode's capacitance, on the condition that this capacitance is not reset inbetween measuring Vs and Vr: if the capacitor is reset inbetween the two sampling instants, their noises are uncorrelated and kTC noise persists. (One sometimes calls this method of readout Double Sampling, DS, in contrast to CDS.

But the following noise sources are not mitigated, or are even promoted, by CDS:

  • second order effects due to pixel gain non-uniformity or non-linearity are not compensated for.
  • uncorrelated temporal white noise originating from before the differencing operation, such as broadband amplifier noise, is multiplied by a factor 1.4 by the differencing operation.
  • all of the downstream noise sources, such as EMI, system noise, discretisation noise etc. are not affected.
  • low frequency MOSFET noise (1/f noise, flicker noise) is reduced only partially, by a factor that is the logarithm of the associated reduction in bandwidth, typically a factor not more than 1...3. In the literature the reduction of 1/f noise is typically over-estimated, or not recognised as such, as the 1/f noise after CDS or DS appears to be "white", which is due to aliasing effects.
  • signal noise, as optical shot noise is in principle not affected by CDS.
  • fixed pattern noise due to dark current non-uniformity.

..: Which approach is the best?

It depends:

  • for a standard-CMOS APS the on-chip implementation of DS is more straightforward than CDS.
  • a major competitor for on-chip CDS is an optimised multiple-order fixed pattern correction, where individual pixel offsets are corrected in a post-processing step. This is typically done in applications requiring the very highest image quality, such as photography.
  • CDS and post-processing offset correction, both off-chip, might be combined.

on-chip DS on-chip CDS off-chip CDS off-chip fixed pattern correction
IC technology standard complex - -
system requirements - - memory and subtractor memory and subtractor
cancels kTC noise? no yes yes no
impact on MOSFET amplifier- and system noise +3dB +3dB +3dB -
compensates static non-uniformities? yes yes yes yes
compensates dark current-induced non-uniformites? no no no yes

In order to decide it is important to estimate the relative importance of the four noise sources, in the light of the application and system at hand. In high quality CCDs kTC noise dominates in low-light situations, otherwise photon shot noise is dominant. In CMOS sensors the cosmetic deficiencies and MOSFET noises are typically dominating. The emphasis then must be on the full-blown correction of fixed pattern noises, and the correction of kTC noise is of somewhat less importance. Therefore on-chip DS and/or off-chip optimised fixed pattern correction are our prime choices. In many applications where the resulting image quality is of prime importance, the image is subject to massive post-processing anyway (e.g. bad pixel correction, RGB processing and enhancing, output formatting or compression): the processing power and memory present in the system can then be employed then for pattern correction without much additional cost.

..: Implementing CDS on-chip

Presenting a pixel's pre-exposure reset level and post-exposure actual signal simultaneously to a subtractor, requires that the pixel memorise one or both of these signals for a certain period of time: analogue pixel memory is needed. Two methods are widely used:

CCD-like pixels (photogate pixels)

Every pixel contains the output stage of a CCD, which is accessed in CDS-fashion. The collection gate/transfer gate essentially acts as a charge packet memory.

  • advantage: conversion on a low capacitance, thus good kTC noise suppression.
  • main drawback: not every CMOS process is compatible with this approach.

Pixels with a local memory element

The reset and/or signal levels are memorised on a local capacitor, accessable with additional switches, so that they are both available at the moment of readout of the pixel.

  • advantage: can be implemented in standard VLSI processes.
  • main drawback: complex pixel, many active elements, large storage capacitor.

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