Controller FV-201 with DSP TigerSharc ADSP-TS201S

High-speed data acquisition system based on TigerSharc video controller FV-201 provides online data capture from MT9M413 sensor running at 66 MHz. The board gets the data from Altera Stratix-II FPGA and provides data control, data distribution and front-end high-speed processing capabilities.

Processor

• Analog Devices dual core ADSP-TS201S TigerSHARC DSP
• 600 MHz, 1.67 ns instruction rate DSP core
• 3.6 GFLOPS (32-bit floating point) or 14.4 GOPS (16-bit fixed point)
• Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
• 24 Mbit on-chip embedded DRAM internally organized in six banks with user-defined partitioning
• Integrated I/O processor with fourteen-channel DMA controller and eight 0.5 GByte/sec LVDS link ports (4 full-duplex link ports)
• Four internal 128-bit wide internal buses providing a total memory bandwidth of up to 38.4 Gbytes per second
• Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
• Assembly and C language programmability

DSP Shared Memory

• Built-in 32 MB SDRAM
• 4 MB ROM memory for booting DSP

Link Ports

• 8 link ports with bandwidth 0.5 GByte/sec (4 full-duplex link ports)

External Connectors

• Controller has 3 high-speed connectors for link port output: 2 in, 1 out / 1 in, 2 out / 1 in, 1 out
• Power supply 5V, 1A

Development Tools

• Analog Devices' VisualDSP++ tools: kernel (VDK), C compiler, assembler, linker, simulator and debugger
• Analog Devices ICE emulators